The use of advanced CMOS technologies, for example the use of 65 nanometer or sub-65 nanometer technologies, and in particular 45 or 32 nanometer technologies, leads to lower and lower supply voltages being used.
An electronic device for protecting from electrostatic discharge comprising a triac and triggering means employing MOS transistors capable, in the presence of a current pulse, resulting for example from an electrostatic discharge, of operating in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the parasitic bipolar transistor, is described in published International Patent Application No. PCT/EP2011/050740 (WO 2011/089179), the disclosure of which is incorporated by reference.
The hybrid operating regime of a MOS transistor was demonstrated in the article by Galy, et al., “Ideal Gummel curves simulation of high current gain vertical NPN BIMOS transistor”, Int. J. Electronics, 1996, Vol. 80 No. 6, 717-726, the disclosure of which is incorporated by reference. This article is a theoretical study carried out on a transistor with a vertical structure having a gate length (channel length) of about a micron and validated by simulations, without any application whatsoever of such hybrid operation being mentioned.
A four-terminal microelectronic component combining the bipolar effect and the MOS effect in a hybrid operating mode, in order to improve current gain, has also been described in French Patent Application No. 2,784,503, the disclosure of which is incorporated by reference. Such a component is presented as being able to withstand ionizing radiation and it is specified, in a general way, that it may be employed in mass-market, aerospace and/or military applications in the digital and analog fields without any application whatsoever of the hybrid operation of the component being mentioned.
The aforementioned published International Patent Application No. PCT/EP2011/050740 teaches that it is particularly beneficial to use this hybrid transistor operating regime especially to produce a device subjected to current pulses, in particular a device for protecting a component from electrostatic discharge, which discharge results in a current pulse between two terminals of the device, the current pulse being caused by a pulsed voltage difference between these two terminals.
This hybrid operation is obtained when the transistor is configured so that the gate of the MOS transistor is biased with a voltage lower than its threshold voltage and when the voltage difference between the substrate and the source of the MOS transistor is positive. This positive voltage difference is for example obtained when the substrate of the MOS transistor, which forms the intrinsic base of the parasitic bipolar transistor, is biased with a non-zero voltage whereas the source of the MOS transistor is grounded.
Provided that the transistor configuration conditions required to obtain this hybrid operation are met, the latter may be observed for relatively large gate lengths, for example 1 micron, though, in this case, the hybrid operation is not particularly applicable industrially.
In contrast, with technology scaling, the base of the parasitic bipolar transistor becomes smaller, particularly for 65 nanometer or sub-nanometer technologies and even more particularly for sub-50 nanometer technologies, for example 45 nanometer and 32 nanometer technologies, making the parasitic bipolar behavior of the MOS transistor more important.
Significant sub-threshold-voltage operation of the MOS transistor and simultaneous operation of the parasitic bipolar transistor then becomes possible, at least temporarily at the start of the current pulse.
Furthermore, with such hybrid operation, the current gain of the bipolar transistor, controlled by the gate voltage of the MOS transistor, may become substantial, even reaching a value as high as twenty or more.
Thus, this hybrid operation allows such a device to be advantageously used as an effective means for triggering a triac providing protection from electrostatic discharge, thereby significantly reducing the triggering threshold of the triac from about 8 volts to about 5 volts.